1. Field of the Invention
The present invention relates to electronic circuits, and, more particularly, to implementation and use of on-chip resistances.
2. Description of the Related Art
In integrated circuits there are great cost savings associated with implementing a circuit element such as a resistor with on-chip components. Transistors are one method of providing on-chip or integrated resistors. For example, in the linear region of the drain curve, a field-effect transistor (FET) behaves like a voltage-controlled resistor. A single FET can provide a linear, voltage-controlled resistance for small signals of either polarity. However, the FET's effective resistance is highly non-linear in that it has a dependence on the drain and source voltages. For example, at low V.sub.DS, an n-channel Metal-Oxide Semiconductor (NMOS) transistor has low resistance, but at high V.sub.DS, an NMOS transistor's resistance increases dramatically. Even within a restricted input voltage swing, a transistor's resistance value can vary greatly and is asymmetric within a range of input voltages. Also, complementary MOS transistors exhibit large variations in performance with process, voltage supply, and temperature conditions. Therefore, although an ideal resistor has exactly the resistance desired and has no voltage dependence on the voltage at the input terminals, actual on-chip resistors only approximate this behavior.
There are several cases in which an accurate, noise immune resistance is desirable. For example, such a resistance is desirable for on-chip low pass filtering of input differential signals for adaptive receiver equalization to compensate for transmission line attenuation. In this example, an exponential moving average of the signal may be desired for use in an equalization scheme where the "tracked" average value is used to follow intersymbol interference caused by channel attenuation.
Also, an accurate, noise-immune resistance is desirable for on-chip termination of fiber channel, gigabit ethernet, firewire, lvds, or in general any high speed differential channel. Also, such a resistance is desirable when components are typically not on-board for cost reasons, when on-chip termination presents better signal integrity for the receiver's eye diagram, or when multiple possible cable impedances imply that the user wants to be able to use a modifiable termination resistance to terminate multiple possible values (e.g. 50 ohms or 75 ohms).
One previous on-chip resistor implementation provides an impedance matching circuit to terminate transmission lines. K. Lee, S. Kim, G. Ahn, D K. Jeong, "A CMOS Serial Link for Fully Duplexed Digital Data Communication," IEEE J. Solid-State Circuits, vol. 30, no. 4, pp. 353-363, April 1995. On-chip voltage controlled resistors (VCR's) are connected between V.sub.DD and the cable ends, which are controlled by the common impedance matching circuit. The impedance matching circuit generates a voltage-controlled resistor control signal which sets the resistance according to an external resistance value. Lee et al. does not compensate for the non-linearity in the resistance. Also, Lee et al. requires a direct current pull-down path to sink the sourced current. Additionally, such a configuration is sensitive to common-mode noise on the input signal and the positive supply.
Another termination scheme is disclosed in R. Mooney, C. Dike, S. Borkar, "A 900Mb/s Bidirectional Signaling Scheme," IEEE J. Solid-State Circuits, vol. 30, no. 12, pp. 1538-1543, December 1995. Because Mooney et al. is digital, the exact termination value is rarely available. The Mooney et al. implementation also does not compensate for the non-linearity of MOS transistors, and is again sensitive to common-mode noise on the input signals, the positive supply and, in addition, the negative supply.